Hiding and masking are two mainstream countermeasures against side channel analysis (SCA) at cell levels.In power analysis, both rely on the fact that variant data transitions consume more distinguishable power than invariant ones.In this letter, we propose a novel scheme based on fluctuating power logic (FPL), which mitigates the side-channel effect by employing cascade voltage logic to fluctuate physical power leakages.This proposed scheme is illustrated by a standard flip-flop which typically behaves as a major power consumer of the circuit.HSPICE based simulation shows that the modified flip-flop is resistant against power analysis at the cost of doubled power dissipation.Our proposal can be further applied to enhance various SCA-resistant logics, such as sense-amplifier based logic (SABL) and wave dynamic differential logic (WDDL).