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As a connection between the process and the circuit design,the device model is greatly desired for emerging devices,such as the double-gate MOSFET.Time efficiency is one of the most important requirements for device modeling.In this paper,an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended,and different calculation methods are compared and discussed.The results show that the calculation speed of the improved model is substantially enhanced.A two-dimensional device simulation is performed to verify the improved model.Furthermore,the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.
As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET.Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Futuremore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.