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提出了一个可用于0.18μmCMOS工艺RF-MOSFET的源漏电阻的可缩放模型。采用了一种直接基于S参数测量的方法来准确提取端口的寄生电阻,该模型充分考虑了各种版图尺寸,如沟道长度,沟道宽度和栅极指头数目等参数的可缩放性。此后,该模型通过不同尺寸的共源连接RFMOSFET的测量和仿真的直流、小信号S参数特性比对,曲线达到了较好的吻合,表明我们的模型是精确而且有效的。
A scalable model of source-drain resistance for a 0.18μm CMOS process RF-MOSFET is proposed. A method based on S-parameter measurements is used to accurately extract the parasitic resistance of the port. This model takes full account of the scalability of various layout dimensions such as channel length, channel width, and gate finger number. After that, the model achieves better agreement by comparing the DC-signal and small-signal S-parameter characteristics of different sizes of common-source RFMOSFET measurement and simulation, which shows that our model is accurate and effective.