在数字电路中,经常碰到同步计数器、非同步计数器,这些计数器有五进制、八进制、十进制等等。而这些计数器是如何设计出来的呢?这就是我们要谈的问题。这里我们主要介绍一种新的设计方法。计数器是由触发器组成的,而触发器有好几种,目前常用的有JK触发器,D触发器和T触发器。为此,我们就以这三种触发器为例,来介绍计数器的设计。一、同步计数器的设计同步计数器的一般设计方法为:其一,根 In digital circuits, often encounter synchronous counter, asynchronous counter, these counters have five, eight, decimal and so on. How are these counters designed? Here is the question we are going to talk about. Here we mainly introduce a new design method. Counter is composed of flip-flop, and flip-flop there are several, currently used JK flip-flop, D flip-flop and T flip-flop. To this end, we will use these three triggers, for example, to introduce the design of the counter. First, the design of synchronous counter Synchronous counter of the general design method: First, the root