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CMOS二进制逻辑受短沟道效应、功率密度及互连约束等条件的限制。非硅多值逻辑计算是克服上述问题的一种有效方案。本研究在碳纳米管场效应管(carbon nanotube field effect transistors,CNTFET)的基础上提出了两种高性能四进制全加单元。该全加单元利用了CNTFET独有的特性,如目标电压阈值可通过调整碳纳米管管径控制、CNTFET具有与p型和n型器件相同的迁移性。通过在Synopsys HSPICE中使用32 nm斯坦福综合CNTFET模型,在多种测试条件下对所述电路单元进行了仿真。与当前水平的四进制全加器相比,本文所采用的设计平均降低延迟32%,所需平均功率、能耗及静态功率分别为现有水平的68%、83%及77%。仿真结果表明,所述设计在生产制程、电压、温度变化、噪声耐受方面具有较好的鲁棒性。
CMOS binary logic is limited by short-channel effects, power density, and interconnect constraints. Non-silicon multi-valued logic calculation is an effective solution to the above problems. In this study, we propose two high-performance quaternary all-add-on elements based on the carbon nanotube field effect transistors (CNTFETs). This all-in-memory unit takes advantage of CNTFET’s unique features such as target voltage threshold control by tuning the CNT nanotube diameter and CNTFETs with the same mobility as p- and n-type devices. The circuit cell was simulated under various test conditions by using a 32 nm Stanford integrated CNTFET model in Synopsys HSPICE. Compared with the current quadruple full adder, the design adopted in this paper reduces the average delay by 32%, and the average power, energy consumption and static power required are 68%, 83% and 77% respectively. The simulation results show that the design has good robustness in terms of manufacturing process, voltage, temperature change and noise tolerance.