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介绍了用法国OMMIC公司 0 2 μmGaAsPHEMT工艺设计的具有 90°可调移相的万兆以太网数据判决芯片的模块及单元电路的结构 ,给出了仿真结果及版图 ,最后给出分析和结论 .该芯片的判决电路采用SCFL (源级耦合晶体管逻辑 )的D触发器结构 ,根据矢量叠加原理设计 ,采用差动电流放大器构成可调移相器 .该芯片可直接用于万兆以太网IEEE 80 2 3ae中 10GBASE R和 10GBASE W的物理媒介配属层的时钟数据恢复模块中 .
This paper introduces the structure of the module and unit circuit of a 10 Gigabit Ethernet data decision chip with a 90 ° adjustable phase shift designed by OMMIC 0 2 μm GaAsPHEMT process. The simulation results and layout are given. Finally, the analysis and conclusions are given. The chip’s decision circuit uses SCFL (source-coupled transistor logic) D flip-flop structure, designed according to vector superposition principle, the use of differential current amplifier constitutes an adjustable phase shifter. The chip can be used directly for 10 Gigabit Ethernet IEEE80 2 3ae 10GBASE R and 10GBASE W Physical Media Affinity Layer Clock Data Recovery Module.