设计了基于逐次逼近式架构的低功耗A/D转换器,该转换器有14/8 bit转换精度2种工作模式,其采样率分别为0~1×105/s和0~2×105/s.低功耗转换器基于0.18μm的互补金属氧化物半导体(CMOS)工艺完成版图设计,版图面积仅为0.64 mm×0.31 mm.转换器在最高性能下的积分非线性(INL)和微分非线性(DNL)最低有效位分别为0.38 LSB和0.33 LSB,电流消耗仅为2 mA. A low power A / D converter based on successive approximation architecture is designed. The converter has two operation modes of 14/8 bit conversion accuracy, the sampling rates are 0 ~ 1 × 105 / s and 0 ~ 2 × 105, respectively / s. The low power converter is based on a 0.18μm Complementary Metal Oxide Semiconductor (CMOS) process to achieve a layout footprint of only 0.64 mm × 0.31 mm. The converter’s integral nonlinearity (INL) and differential The least significant bits of the non-linear (DNL) are 0.38 LSB and 0.33 LSB, respectively, with a current consumption of only 2 mA.