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设计了一款用于高速CMOS图像传感器的多列共享列并行流水线逐次逼近模数转换器.八列像素共享一路pipeline-SAR ADC,从而使得ADC的版图不再局限于二列像素的宽度,可以在16列像素宽度内实现.该模数转换器采用了异步控制逻辑电路来提高转换速度.半增益数模混合单元电路被用于对第一级子ADC的余差信号放大,同时被用于降低对增益数模混合单元电路中运放性能的要求.相关电平位移技术也被用于对余差信号进行更精确的放大.整个pipeline-SAR ADC第一级子ADC精度为6-bit,第二级子ADC为7-bit,两级之间存在1-bit冗余校准,最终实现12-bit精度.输入信号满幅电压为1 V.该8列共享并行处理的pipeline-SAR ADC在0.18 μm 1P4M工艺下制造实现,芯片面积为0.204 mm2.仿真结果显示,在采样频率为8.33 Msps,输入信号频率为229.7 kHz时,该ADC的信噪失真比为72.6 dB;在采样频率为8.33 Msps,输入信号频率为4.16 MHz时,该ADC的信噪失真比为71.7 dB.该pipeline-SAR ADC的电源电压为1.8 V,功耗为4.95 mW,功耗品质因子(FoM)为172.5 fJ/conversion-step.由于像素尺寸只有7.5 μm,工艺只有四层金属,因此这款12-bit多列共享列并行流水线逐次逼近模数转换器非常适用于高速CMOS图像传感器系统.“,”A multiple-columns-shared-parallel pipelined successive approximation register (SAR) analog-to-digital converters (ADC) was presented for high speed CMOS image sensors (CIS) application. As the pixels in 8 columns shared one pipeline-SAR ADC, the layout was no longer restricted to double pixel pitches, and can be implemented within 16 pixel pitches. Asynchronous logic was implemented to improve the conversion speed of multiple-columns-shared-parallel pipeline-SAR ADC. A half-gain multiplying digital-to-analog converter (MDAC) was used for the residue amplification to relax the requirements for the operational amplifier (opamp), and correlated level shift technique was also used for more precise amplification. The 12-bit resolution was divided by 6-bit coarse and 7-bit fine SAR sub-ADC with 1-bit stage redundancy calibration between coarse and fine steps. Input full scale voltage was 1 V. The ADC was designed in 0.18 μm 1P4M CIS process, and occupied 0.204 mm2for 8 columns. The simulated results of the ADC showed a SNDR of 72.6 dB with a 229.7 kHz input and 71.7 dB with a 4.16 MHz input at 8.33 Msps. It dissipated 4.95 mW at 1.8 V supply and the FoM was 172.5 fJ/conversion-step. Because the pixel pitch is only 7.5 μm and the process has only 4 metals, this proposed 12-bit multiple-columns-shared-parallel pipeline-SAR ADC is quite suitable for the high speed CIS.