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简介——破坏读出单管MOS存贮单元的读数信号随单元面积减小而减小。要达到必要小的单元面积,必需具有大的特殊电容的器件作为存贮电容器,还需要灵敏的再生放大器和补偿噪音的阵列。 对于用硅栅工艺的单元布局设计,存贮电容器建议采用电场感应的非平衡反型层作为一个电极。 提出一个门控触发器作为一个灵敏的再生放大器,它的两个输入结点各连接一条位线。这样得到的对称阵列不但是高度灵敏的(输入电压差的不可辨区大约定晶体管阀值电压的0.3)和与制造工艺参数不相关的,而且容许在触发器的每边用一条假的字线(带有假的存贮单元)进行噪音补偿。 不同的单元和再生电路已经用硅栅工艺实现。面积为1600微米~2(2.6密耳)~2的存贮单元已经成功地进行工作,读/写周期时间为350毫微秒(存贮电容为0.134微微法,每条位线64个单元或每个放大器128个单元的位线电容为0.32微微法)。
Introduction - Destruction The readout of single MOS memory cells decreases as the cell area decreases. To achieve the requisite small cell area, devices that must have large, special capacitances as storage capacitors also require sensitive regenerative amplifiers and arrays that compensate for noise. For cell layout designs using silicon gate technology, storage capacitors are recommended to use an electric field-sensing unbalanced inversion layer as one electrode. A gated trigger is proposed as a sensitive regenerative amplifier with two input nodes each connected to a bit line. The symmetrical array thus obtained is not only highly sensitive (the unidentifiable area of the input voltage difference is about 0.3 of the threshold voltage of the transistor) but also irrelevant to the manufacturing process parameters and allows the use of a dummy word line (With fake memory cells) for noise compensation. Different cells and regenerative circuits have been implemented using silicon gate technology. Memory cells having an area of 1600 to 2.6 (2.6 mils) ~ 2 have been successfully operated with a read / write cycle time of 350 nanoseconds (0.134 pF for storage capacitance, 64 cells per bitline or 128 cells per amplifier bitline capacitance of 0.32 pico-method).