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利用截止频率为49GHz的0.18-μm CMOS工艺,设计实现了11.6-GHz锁相环电路.该电路由模拟乘法鉴相器、单极点低通滤波器及采用可变负电阻负载的三级环形振荡器构成.在片晶圆测试表明,该芯片在输入速率为11.6GHz、长度为231-1伪随机序列的情况下,恢复时钟的均方根抖动为2.2ps.锁相环的跟踪范围为250MHz.环形振荡器在偏离中心频率为10MHz处的单边带相位噪声为-107dBc/Hz.在锁定条件下,锁相环在偏离中心频率为10MHz处的单边带相位噪声为-99dBc/Hz.芯片面积为0.47mm×0.72mm,在1.8-V电源供电下,功耗为164mW.
An 11.6-GHz PLL is designed and implemented using a 0.18-μm CMOS process with a cutoff frequency of 49GHz.The circuit consists of an analog multiplier phase detector, a single-pole low-pass filter and a three-stage ring oscillator with a variable negative resistance load Chip wafer test showed that the chip in the input rate of 11.6GHz, the length of the 231-1 pseudo-random sequence, the recovery clock rms jitter 2.2ps. Phase-locked loop tracking range of 250MHz The ring oscillator has a single-sideband phase noise of -107 dBc / Hz at a center frequency of 10 MHz and a single-sideband phase noise of -99 dBc / Hz at a 10 MHz offset center frequency from the phase-locked loop at lock-out. Chip area of 0.47mm × 0.72mm, 1.8-V power supply, the power consumption of 164mW.