本文介绍一种采用相同半导体震荡器模块阵列产生一些锁相时钟信号的时钟系统。当采用3f+1模块时,若 f 个出故障后,锁相至少保持2f+1个锁相信号。如果出故障的不多于 f 个,那么局部调整电路就把3f+1时钟信号变成锁相局部时钟信号。已经制成模型并进行了测试,对采用比较或表决方式来达到容错的系统来讲,这个系统为它提供了可靠的同步。 This article presents a clock system that generates some of the phase-locked clock signals using the same array of semiconductor oscillator modules. When using 3f + 1 module, if f fails, the phase-locked to maintain at least 2f +1 phase lock signal. If there are no more than f failures, the local regulation circuit turns the 3f + 1 clock signal into a phase locked local clock signal. It has been modeled and tested, and the system provides a reliable synchronization of systems for comparison or voting to achieve fault tolerance.