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设计了一种用于超高速A/D转换器的时钟稳定电路。利用全差分连续时间积分器将差分时钟信号的占空比量化为电压信号,再通过跨导放大器产生控制电流来调整输出时钟的共模电平,达到调整输出时钟占空比的目的。电路采用0.18μm标准CMOS工艺进行设计,工作电压为1.8V,在2GHz的最高时钟频率下,将占空比为20%~80%的输入时钟信号调整为(50±1)%,输出时钟抖动小于132fs,具有抑制时钟抖动的能力。
A clock stabilization circuit designed for very fast A / D converters is designed. The duty cycle of the differential clock signal is quantized into a voltage signal by using a fully differential continuous time integrator and then the control current is generated by the transconductance amplifier to adjust the common mode level of the output clock to achieve the purpose of adjusting the duty cycle of the output clock. The circuit is designed with a 0.18μm standard CMOS process and operates at 1.8V. Adjusting the input clock signal with a duty cycle of 20% -80% to (50 ± 1)% at a maximum clock frequency of 2GHz, the output clock jitter Less than 132fs, with the ability to suppress clock jitter.