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本工作模拟仿真了Si/SiGe/SOI量子阱p-MOSFETs的电学性能,重点分析了Si-cap层厚度对Ge的层间互扩散的影响。依据本文的仿真模型,Si-cap层越薄,越有利于形成Si/SiGe突变异质结,并有利于形成势垒更深的量子阱,这有利于将更多的空穴限制在SiGe层中,而不是进入厚的Si-cap层中。空穴在SiGe层中的迁移率显著高于在Si-cap层中的迁移率,从而提高了器件性能。此外,较薄的Si-cap层有利于在SiGe层中形成更高的沟道电场,从而提高器件的开启电流。
This work simulates the electrical properties of Si-SiGe / SOI quantum well p-MOSFETs, and focuses on the influence of the thickness of Si-cap layer on the inter-layer diffusion of Ge. According to the simulation model in this paper, the thinner the Si-cap layer, the more conducive to the formation of Si / SiGe mutant heterojunction, and help to form a deeper barrier quantum barrier, which is conducive to more holes limited to the SiGe layer Rather than into a thick Si-cap layer. The mobility of holes in the SiGe layer is significantly higher than that in the Si-cap layer, thereby improving the device performance. In addition, the thinner Si-cap layer facilitates the formation of a higher channel electric field in the SiGe layer, thereby increasing the turn-on current of the device.