介绍了可编程逻辑器件PLD的主要器件—通用阵列逻辑GAL的结构特点和主要性能特点 ,并阐述了用GAL设计八位二进制可逆同步计数器的方法 .同时介绍一种通用逻辑设计软件—CUPL语言 .文中着重介绍了八位二进制可逆同步计数器的功能特点及其用GAL设计的方法 .这对于经常使用GAL进行数字系统设计的同行 ,具有较大的借鉴意义 . This paper introduces the structure and main performance characteristics of GAL, the main device of programmable logic device (PLD), and describes the method of designing 8-bit binary synchronous counter by GAL.A general logic design software-CUPL language is also introduced. The paper mainly introduces the functional characteristics of 8-bit binary reversible synchronous counter and its design method with GAL, which is of great reference to the counterparts who often use GAL to design digital system.