数字滤波器在数字系统中起着举足轻重的作用,笔者利用一片单稳态多谐振荡器芯片74LS123构或一简单可靠的数字滤波器。图中74LS123是两个独立的单稳态多谐振荡器芯片,每个输入脉冲将使单稳多谐振荡器的输出(13端和5端)在预定的时间间隔内变成高电平,它的定时周期的长短由电阻和电容决定,13端输出的定时周期T_1由R_1、C_1决定,T_1≈0.31 R_1C_1=1/f_1,5端输出的定时周期T_2由R_2、C_2决定,T_2≈0.31R_2C_2=/1f_2。如果输入脉冲的周期T(=1/f)比单稳态多谐振荡器的定时周期短,则单稳态振荡器的输出端出现连续的高电平,这个高电平输入到D端通过CP输入端使触发器置位,Q输出高电平,如果T大于单稳态的定时周期,则触发器Q端输出低电平。最后利用这些Q和(?)端打开不同的与门(F_3、F_4、F_5、F_6和F_7),分别让不同频率的输入信号在不同的与门输出,从而构成了几组数字滤波 Digital filter plays a decisive role in the digital system, I use a monostable multivibrator chip 74LS123 structure or a simple and reliable digital filter. The figure 74LS123 is two independent monostable multivibrator chips, each input pulse will make monostable multivibrator output (13 end and 5 end) in a predetermined time interval becomes high, The length of its timing period is determined by the resistance and the capacitance. The timing period T_1 output by the 13 terminal is determined by R_1 and C_1. T_1≈0.31 R_1C_1 = 1 / f_1 The timing period T_2 output by the 5 and 5 terminals is determined by R_2 and C_2, T_2≈0.31 R_2C_2 = / 1f_2. If the period of the input pulse T (= 1 / f) is shorter than that of the monostable multivibrator, the output of the monostable oscillator appears continuously high, and this high level is input to the D terminal The flip-flop is set at the CP input and the Q output is high. If T is greater than the one-shot timer, the Q output of the flip-flop is low. Finally, we use these Q and (?) Terminals to open different AND gates (F_3, F_4, F_5, F_6 and F_7) to let the input signals of different frequencies output at different AND gates, respectively, to form several groups of digital filters