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支持IEEE1149.1标准的边界扫描芯片的广泛应用和可测性设计(DFT)的研究,使边界扫描测试技术得到广阔的发展。我们以边界扫描测试技术为基础设计集成电路(IC)测试平台,并对许多复杂的IC进行测试。该平台不需要昂贵的仪表、设备,而是通过边界扫描芯片的特点产生并捕获测试信号,并且还具有很高的测试覆盖率。同时也根据在测试开发中遇到的问题,对可测性设计提出一些建议。
Extensive applications and design of testable designs (DFTs) that support the IEEE1149.1 standard for boundary-scan chips have seen broad advances in boundary-scan-test techniques. We design integrated circuit (IC) test platforms based on boundary-scan test techniques and test many complex ICs. The platform does not require expensive instruments, equipment, but through the characteristics of the boundary scan chip to generate and capture test signals, but also has a high test coverage. At the same time, some suggestions on testability design are also put forward based on the problems encountered in test development.