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首先阐述了(2,1,2)卷积码的原理和维特比(Viterbi)译码的实现过程,并对编码器、Viterbi译码器进行了现场可编程门阵列(FPGA)设计和实现。仿真表明了设计模块的正确性,而且能够满足速度和精度的要求。其次对最大自由距离的非恶性卷积码在高斯白噪声(AWGN)信道下的误码率性能进行分析,通过Matlab仿真表明卷积码具有很强的纠错能力,当卷积码的约束长度增大时,其误码率逐渐降低。结果表明所设计的卷积码译码器输出时延小,占用资源较少。具有一定的实用价值。
Firstly, the principle of (2,1,2) convolutional codes and the implementation of Viterbi decoding are expounded. The design and realization of field programmable gate arrays (FPGAs) for encoders and Viterbi decoders are described. Simulation shows that the design of the module is correct, but also to meet the speed and accuracy requirements. Secondly, the BER performance of non-malignant convolutional codes with maximum free distance under Gaussian white noise (AWGN) channel is analyzed. The Matlab simulation shows that convolutional codes have strong error correction ability. When the constraint length of convolutional codes When it increases, its bit error rate gradually decreases. The results show that the designed convolutional code decoder has small output delay and less resource consumption. Has a certain practical value.