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第一阶段用3微米的设计规则开发了高速双极型晶体管和高速CMOSFET的兼容技术。采用具有N~+型掩埋层的外延片。用N阱硅栅CMOSFET兼容多晶硅掺杂发射极源（DOPOS）结构的双极型晶体管来实现工艺的兼容。用越来越简化工艺作为批量生产控制性的某种器件工艺。 双极型晶体管的截止频率f_T=2～4GH2。CMOS倒相器的传输延迟时间C_（pd）=1·2ns等所得到各种的特性是兼容技术的重要目标,完全能够达到分立器件的性能。考虑开发缩小到2微米规则的技术将作为将来第二阶段的发展方向。
The first stage developed a compatible technology for high-speed bipolar transistors and high-speed CMOSFETs using a 3-micron design rule. Epitaxial wafer with N ~ + type buried layer is used. The process is compatible with N-well Si-gate CMOSFET-compatible polysilicon-doped emitter-source (DOPOS) bipolar transistors. A device process that uses more and more simplified processes as a control of mass production. The bipolar transistor cut-off frequency f_T = 2 ~ 4GH2. CMOS inverter transmission delay time C_ (pd) = 1. 2ns, etc. The resulting variety of features is an important goal of compatible technology, fully able to achieve the performance of discrete devices. Consider developing techniques that shrink to 2 micron rules as the next phase of development.