【摘 要】
：
The high speed potential of I.C.components can be exploited by shortening the pipeline clock period.Although there are some factors which dominate the shorteni
【机 构】
：
Institute of Computing Technology Academia Sinica,Institute of Computing Technology,Academia Sinica,
【出 处】
：
Journal of Computer Science and Technology
论文部分内容阅读
The high speed potential of I.C.components can be exploited by shortening the pipeline clock period.Although there are some factors which dominate the shortening,the design of an experimental computeremploys the principle of maximum time difference at the system level to determine the clock period and theintegrated consideration of architecture,logic design and engineering layout to achieve a system clock periodof 9.8 ns using conventional ECL chips of 2ns gate delay.The multiplier in this model,which is constructedwith 0.7 ns gate delay chips,can work at a cloek period of 5.5 ns.
The high speed potential of ICcomponents can be exploited by shortening the pipeline period. Although there are some factors which dominate the shortening, the design of an experimental computeremploys the principle of maximum time difference at the system level to determine the clock period and theintegrated consider of architecture, logic design and engineering layout to achieve a system clock period of 9.8 ns using conventional ECL chips of 2ns gate delay. multiplier in this model, which is constructed with 0.7 ns gate delay chips, can work at a cloek period of 5.5 ns .
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