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对于状态数和输入变量数都不太大的同步时序逻辑网络的设计问题,本文提出可在状态转移图上进行图上作业来实现状态合并。状态转移图中各状态用适当编码表示后,还可通过图上作业求出表示各触发器置位,复位条件的逻辑函数,进而确定各触发器的激励函数。这种设计法省略了作隐含表、状态转移表等手续,使设计得到简化。文中举例说明这种设计法。
For the problem of design of synchronous sequential logic network, which has not too many states and input variables, this paper proposes to realize the state combination by graphically working on the state transition graph. After each state in the state transition diagram is represented by an appropriate code, a logic function indicating each of the flip-flop setting and reset conditions can also be obtained from the operation on the graph to determine the excitation function of each flip-flop. This design method omitted for hidden form, status transfer form and other procedures, to simplify the design. The article illustrates this design method.