产业资深顾问Handel Jones认为,半导体业者应该尽速转移14纳米FD-SOI(depleted silicon-on-insulator)制程,利用该技术的众多优势…半导体与电子产业正努力适应制程节点微缩至28纳米以下之后的闸成本(gate cost)上扬;在制程微缩同时,每单位面积的逻辑闸或电晶体数量持续增 Handel Jones, a senior consultant for the industry, believes that the semiconductor industry should speedily shift its 14-nanometer FD-SOI process to take advantage of the many advantages of the technology ... The semiconductor and electronics industries are struggling to adapt their process nodes down to 28 nanometers The gate cost goes up. At the same time as the manufacturing process is shrinking, the number of logic gates or transistors per unit area continues to increase