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提出了一种用于CMOS图像传感器的数字双采样10位列级模数转换器.比较器采用失调消除技术,数字双采样通过加/减计数器实现,使复位信号和像素信号的量化结果在数字域做差,消除了像素输出产生的固定模式噪声;列电路由一个比较器、一个计数器和一个锁存选通器组成.采用GSMC 0.18μm标准CMOS工艺对电路进行设计,一个完整的A/D转换时间为11μs,使用Cadence spectre进行仿真,结果表明:ADC的信噪失真比为57.86dB,有效位数9.32,列电路功耗为58.24μW,由比较器的失调和延迟产生的误差可以减小50%.
A digital double-sampling 10-bit ADC for CMOS image sensor is proposed.It uses offset cancellation technology, digital double sampling is realized by up / down counter, and the result of quantization of reset signal and pixel signal is displayed in digital The field is poor, eliminating the fixed-mode noise generated by the pixel output. The column circuit consists of a comparator, a counter and a latch gater. The circuit is designed using a standard CMOS process of GSMC 0.18μm with a complete A / D The conversion time is 11μs. Simulation results using Cadence specter show that the ADC has a signal-to-noise distortion ratio of 57.86dB and an effective median of 9.32. The power consumption of the column circuit is 58.24μW. The error caused by the offset and delay of the comparator can be reduced 50%.