本文采用VHDL语言完成了基于改进型全数字锁相环(ADPLL)的频率合成器设计与实现。本设计使用自适应数字分频器克服了锁相环同步带的限制。频率合成器的输入信号频率从1Hz到10MHz范围,输出信号相位以输入信号为基准,输出信号频率从1Hz到10MHz由用户设定,频率分辨率为1Hz。输出信号与输入信号的最大相差可控,输出信号频率的最大频差可控。 In this paper, VHDL language based on the improved all-digital phase-locked loop (ADPLL) -frequency synthesizer design and implementation. The design uses an adaptive digital divider to overcome the PLL’s timing band limit. Frequency synthesizer input signal frequency from 1Hz to 10MHz range, the output signal phase to the input signal as a reference, the output signal frequency from 1Hz to 10MHz set by the user, the frequency resolution of 1Hz. The maximum difference between the output signal and the input signal is controllable, and the maximum frequency difference of the output signal frequency is controllable.