Delay consideration has been a majorissue in design and test of high performance digital circuits. Theassumption of input signal change occurring only when all
Recently, Giordano and Martelli (1994) proposed two newcumulative variants of Reiters default logic (DL): Commitment toAssumptions Default Logic (CADL) and Quas
A new approach to deciding quasi-reducibility is proposed by introducing witnesses. Furthermore, an algorithm for constructingwitnessed test sets of left-linear