设计了一款基于延迟锁定环(DLL)和同步计数器结构的10位片上时间数字转换电路(TDC)。采用两步层级设计方法,利用同步计数器进行粗量化输出6位二进制码,量化时钟周期的整数倍,再利用高性能差分DLL输出16路固定相移的时钟信号采样,精量化不足一个时钟周期的部分,输出4位温度计码。该结构可以提供较好的精度、动态范围以及转换速度,与传统的子门延时TDC相比,该结构TDC占用的芯片面积更少,转换速度更高,受工艺、电压及温度影响更少。仿真结果表明:该TDC具有LSB 62.5ps和MSB 64ns的动态范围,满足一般与时间相关的单光子计数需要。 A 10-bit on-chip time-to-digital conversion circuit (TDC) based on a delay locked loop (DLL) and synchronous counter structure is designed. A two-step hierarchical design method is adopted, the 6-bit binary code is coarsely quantized by the synchronous counter, the integral multiple of the clock cycle is quantified, and then 16 high-performance differential DLLs are used to output the 16 fixed-phase shifted clock signals and the precision is less than one clock cycle Part, the output 4-bit thermometer code. The structure can provide better accuracy, dynamic range and conversion speed. Compared with the traditional TDR TDC, the TDC occupies less chip area and has higher conversion speed and less influence of process, voltage and temperature . The simulation results show that the TDC has the dynamic range of LSB 62.5ps and MSB 64ns to meet the general time-correlated single photon counting needs.