The effects of stage numbers on power dissipation of pipeline analog-to-digital converter (ADC) are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm (MCNA) is first introduced,and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio (Rp). For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.