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随着半导体工艺的不断发展,器件的特征尺寸在不断缩小,栅氧化层也越来越薄,使得器件受到静电放电破坏的概率大大增加。为此,设计了一种用于保护功率器件栅氧化层的多晶硅背靠背齐纳二极管ESD防护结构。多晶硅背靠背齐纳二极管通过在栅氧化层上的多晶硅中不同区域进行不同掺杂实现。该结构与现有功率VDMOS制造工艺完全兼容,具有很强的鲁棒性。由于多晶硅与体硅分开,消除了衬底耦合噪声和寄生效应等,从而有效减小了漏电流。经流片测试验证,该ESD防护结构的HBM防护级别达8 kV以上。
With the continuous development of semiconductor technology, the feature size of the device is shrinking, and the gate oxide layer is also getting thinner and thinner, making the probability of the device being destroyed by electrostatic discharge greatly increased. To this end, a polysilicon back-to-back Zener diode ESD protection structure for protecting the gate oxide of a power device is designed. Polysilicon back-to-back Zener diodes are implemented by different doping in different regions of polysilicon on the gate oxide. The structure is fully compatible with the existing power VDMOS manufacturing process and has strong robustness. Since polysilicon and bulk silicon separate, eliminating the substrate coupling noise and parasitic effects, thus effectively reducing the leakage current. The chip test proved that the ESD protection structure has an HBM protection level of over 8 kV.