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本文拟设计一种工作在200mv电源电压下的大容量7T亚阈值域SRAM位单元。双端写入和单端读取保证了不损耗可写性的情况下,SRAM位单元高读取的静态噪声容限(SNM)。结合局部动态阈值MOSFET技术,7 T SRAM容量大、效率稳健,设计不容易受小面积的工艺变化影响。对比6 T和8 T的SRAM位单元,提出位单元有四个方面需要改善:(1)5.13%和7.27%较大的维持容限;(2)80.60%和51.92%较大的维持容限标准差;(3)28.58%和46.28%位单元面积的减少;(4)每根位线上16X和8X的位单元数(200mV)。
This article intends to design a large-capacity 7T sub-threshold SRAM bit cell operating at 200mV supply voltage. Double-ended writes and single-ended reads guarantee a static read noise floor (SNM) for SRAM cells that are readable without loss of writeability. Combined with local dynamic threshold MOSFET technology, the 7 T SRAM has large capacity and robustness, and the design is not susceptible to small-area process variations. Comparing SRAM cell locations of 6 T and 8 T, there are four proposed bit cell improvements that need to be addressed: (1) a larger sustain margin of 5.13% and 7.27%; (2) a larger sustain margin of 80.60% and 51.92% Standard deviation; (3) a reduction of 28.58% and 46.28% of the bit cell area; and (4) the number of bit cells of 16X and 8X (200mV) per bit line.