针对处理器与UART接口速度不匹配,设计了一种内置先进先出存储器全双工通用异步收发器,提高了处理器和UART接口的效率。该设计包含发送模块、接收模块、波特率发生器模块、数据存储模块和总线接口模块。整个设计基于Quartus II平台,使用VHDL语言编程实现。经软件仿真,验证了该设计的正确性和可行性。 Aiming at the speed mismatch between UART and UART, a full-duplex, first-in-first-out universal asynchronous receiver (UART) transceiver is designed, which improves the efficiency of the processor and UART interface. The design includes the transmit module, receive module, baud rate generator module, data storage module and bus interface module. The entire design is based on the Quartus II platform and is programmed using VHDL. The software simulation shows that the design is correct and feasible.