论文部分内容阅读
设计了一种12位4MS/s的异步逐次逼近型模数转换器(SAR ADC)。采用一种既能节省开关动态功耗又能减小电容面积的开关切换策略,与传统结构相比,开关动态切换功耗节省了95%,电容总面积减小了75%。为了避免使用高频时钟,采用了异步控制逻辑,采样开关采用栅压自举开关以便提高ADC的线性度,动态锁存比较器的使用减小了静态功耗,片上集成了电压参考电路和相关驱动电路。基于SMIC 0.18μm CMOS工艺,在1.8V电源电压和4 MS/s转换速率条件下,经后仿真得到ADC的信号噪声失真比SNDR为70.2dB,功耗仅为0.9 mW,品质因素FOM为109fJ/conversion-step。
A 12-bit 4MS / s asynchronous successive approximation analog-to-digital converter (SAR ADC) is designed. Using a switching strategy that saves both switching dynamic power and capacitive area, switching power savings of up to 95% and switching capacitance of 75% are reduced compared to conventional architectures. In order to avoid the use of high-frequency clock, the use of asynchronous control logic, sampling switch gate voltage bootstrap switch in order to improve the linearity of the ADC, dynamic latch comparator to reduce the static power consumption, the integrated voltage reference circuit and related Drive circuit. Based on the SMIC 0.18μm CMOS process, the signal noise distortion ratio (SNR) of the ADC is 70.2dB, the power consumption is only 0.9 mW, and the quality factor FOM is 109fJ / s under 1.8V supply voltage and 4 MS / s slew rate. conversion-step.