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构建的两种适用于谐振时钟的CMOS触发器结构:SAER(Sense Amplifier Energy Re-covery)和SDER(Static Differential Energy Recovery),克服了传统触发器在谐振时钟触发下短路功耗大的问题,适用于对时钟网络实现能量回收与节省的系统。在SMIC 0.13μm工艺下进行功耗和时序参数仿真,对比应用在同样谐振时钟下的传统主从结构触发器MSDFF(Master-Slave DFlip-flop)和高性能触发器HLFF(Hybrid Latch Flip-flop),SAER在测试的频率范围内保证高性能时序参数的同时,实现了三分之一以上的功耗节省。
Two kinds of CMOS flip-flop structure suitable for resonant clock are constructed: SAER (Sense Amplifier Energy Re-covery) and SDER (Static Differential Energy Recovery), which overcomes the problem that the traditional flip- In the clock network to achieve energy recovery and savings of the system. The power consumption and timing parameters are simulated under the SMIC 0.13μm process. Compared with the traditional master-slave structure trigger MSDFF (Master-Slave DFlip-flop) and the high-performance flip-flop HLFF (Hybrid Latch Flip-flop) SAER achieved more than a third of power savings while maintaining high-performance timing parameters over the test frequency range.