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基于SMIC 65nm CMOS工艺,设计了一种10位10 MS/s逐次逼近型模数转换器(SAR ADC)。采用全差分的R-C组合式DAC网络结构进行设计,提高了共模噪声抑制能力和转换精度。与全电容结构相比,R-C组合式DAC网络结构有效减小了版图面积。DAC中各开关的导通采用对称的开关时序,使比较器差分输入的共模电平保持为固定值,降低了比较器的失调电压,提高了ADC的线性度。在2.5V模拟电源电压和1.2V数字电源电压下,使用Spectre进行仿真验证,测得DNL为0.5LSB,INL为0.8LSB;在输入信号频率为4.990 2 MHz,采样频率为10 MHz的条件下,测得电路的有效位数为9.63位,FOM为0.04pJ/conv。
Based on the SMIC 65nm CMOS process, a 10-bit, 10 MS / s successive-approximation analog-to-digital converter (SAR ADC) is designed. Using fully differential R-C modular DAC network structure design, improved common mode noise rejection and conversion accuracy. Compared with the whole capacitor structure, R-C modular DAC network structure effectively reduces the layout area. The conduction of each switch in DAC adopts the symmetrical switching sequence, keeps the common mode level of the comparator differential input at a fixed value, reduces the offset voltage of the comparator, and improves the linearity of the ADC. Under the 2.5V analog supply voltage and 1.2V digital supply voltage, Spectre was used to simulate and verify that the DNL was 0.5LSB and the INL was 0.8LSB. Under the condition of input signal frequency of 4.990 2 MHz and sampling frequency of 10 MHz, The effective number of bits measured circuit 9.63, FOM 0.04pJ / conv.