论文部分内容阅读
基于MOS管在亚阈值区、线性区和饱和区的不同导电特性,采用TSMC 0.18μm CMOS工艺,设计了一种全MOS结构的电压基准源。为了改进核心电路,通过设计并优化预抑制电路,使整个电路实现了高电源电压抑制比的输出电压。对电路进行仿真,当电源电压大于1.5V时,电路进入正常工作状态;在1.8V电源电压下,-20℃~120℃范围内,温度系数为1.04×10-5/℃,该电压基准源的输出电压为0.688 V;低频时,电源电压抑制比达到-159.3dB,在1MHz时电源电压抑制比为-66.8dB,功耗小于9.83μW。该电压基准源能应用于高电源电压抑制比、低功耗的LDO电路中。
Based on the different conduction characteristics of MOS transistors in subthreshold, linear and saturation regions, a voltage reference of full-MOS structure was designed using TSMC 0.18μm CMOS technology. In order to improve the core circuit, by design and optimization of pre-suppression circuit, the entire circuit to achieve a high supply voltage rejection ratio of the output voltage. The circuit simulation, when the supply voltage is greater than 1.5V, the circuit into the normal working condition; at 1.8V supply voltage, -20 ℃ ~ 120 ℃ range, the temperature coefficient of 1.04 × 10-5 / ℃, the voltage reference source Of the output voltage of 0.688 V; low frequency, the supply voltage suppression ratio of -159.3dB, the supply voltage suppression ratio of -66.8dB at 1MHz, power consumption is less than 9.83μW. The voltage reference can be applied to high power supply voltage rejection ratio, low-power LDO circuit.