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数据的串并转换与字节对齐是高速串行数据通信的一个重要环节.为了使串并转换后输出的并行数据是一个完整字节,设计了一种基于FPGA的高速数据串并转换及字节对齐方法.首先在数据中嵌入8B/10B编码中的K28.5同步码,然后将数据串化发送.用Verilog HDL语言设计了串并转换模块和码形检测模块.串并转换模块负责产生并行时钟并将串行数据并行化后进行输出.实现了1∶10的串并转换以及并行数据字节比特偏移的检测和调整的功能.通过对不同传输速率下的数据进行实验验证,结果表明,该方案能满足高速串行数据通信的要求,减少了硬件电路的设计复杂程度.
Data serial-to-parallel conversion and byte alignment is an important part of high-speed serial data communication.To make parallel data output after serial-parallel conversion is a complete byte, an FPGA-based high-speed data serializer and word conversion Section alignment method, firstly embeds the K28.5 synchronization code in the 8B / 10B encoding into the data, and then sends the data in serial. The serial-parallel conversion module and the pattern detection module are designed by Verilog HDL language. The serial-parallel conversion module is responsible for generating Parallel clock and parallel serial data output after the realization of the serial and parallel conversion and parallel data byte bit offset detection and adjustment functions.According to the experimental data at different transmission rates, the results It shows that the scheme can meet the requirements of high speed serial data communication and reduce the design complexity of the hardware circuit.