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This paper proposes a single channel, 6-bit 230-MS/s asynchronous successive approximation register analog-to-digital converter(ADC) in an SMIC 65 nm CMOS technology. Through adopting the modified2 bits/stage asynchronous control logic, the presented ADC actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS/s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ/step at 1 V supply voltage.
This paper proposes a single channel, 6-bit 230-MS / s -crossover approximation register analog-to-digital converter (ADC) in an SMIC 65 nm CMOS technology. The actualizes a peak 40.90-dB spurious-free dynamic range and 29.05-dB signal-to-noise and distortion ratio at 230-MS / s sampling rate. Utilizing the dynamic comparator without the preamplifier, this work attains low-power design with only 0.93 mW power consumption and accomplishes a figure of merit of 174.67 fJ / step at 1 V supply voltage.