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随着集成度的不断提高,集成电路的绝缘层越来越薄。如CMOS器件绝缘层的典型厚度约为0.1μm,其相应的耐击穿电压在80～100V间。当器件特征尺寸进人深亚微来时,栅氧化层厚度仅为数纳米,而器件工作的电源电压却不宜降低,这使栅氧化层工作在较高的电场强度下,栅氧化层的抗电性能成为一个突出的问题。往往一个能量不算大的电磁脉冲,就可以让集成电路的栅氧击穿,将直接导致MOS器件的失效。
With the continuous improvement of integrated circuits, the insulation of integrated circuits is getting thinner and thinner. For example, the typical thickness of a CMOS device insulating layer is about 0.1 μm, and the corresponding breakdown voltage is between 80 and 100V. When the device feature size into deep sub-micro, the gate oxide thickness of only a few nanometers, and the device power supply voltage should not be reduced, which makes the gate oxide layer operating at higher electric field strength, the gate oxide resistance Performance has become a prominent issue. Often an energy is not large electromagnetic pulse, you can let the integrated circuit gate oxide breakdown, will directly lead to MOS device failure.