基于SMIC 0.13μm CMOS工艺,设计了一种锁定频率范围为0.25~1.25GHz的低杂散锁相环频率合成器。该电路采用一种改进的高精度电荷泵,以减小电荷共享、电流失配等非理想效应,降低了相位误差,减少了输出信号的参考杂散;采用压控电阻器作为延迟单元,设计了一种输出频率广、相位噪声低的压控振荡器。Spectre仿真显示,输出电平在0.3~1.1V范围时,电荷泵的充放电电流失配仅为0.2%,锁相环锁定后的杂散小于-90dBm,满足了低杂散的设计要求。 Based on SMIC 0.13μm CMOS technology, a low spurious PLL frequency synthesizer with a locked frequency range of 0.25 ~ 1.25GHz was designed. The circuit uses an improved high-precision charge pump to reduce non-ideal effects such as charge sharing and current mismatch, reducing the phase error and reducing the reference spurs of the output signal. Using a voltage-controlled resistor as the delay unit, A wide output frequency, low phase noise voltage-controlled oscillator. Specter simulation shows that the charge-discharge current mismatch of the charge pump is only 0.2% when the output level is in the range of 0.3-1.1V, and the spurious lock of the PLL is less than -90dBm, which meets the design requirement of low spurious.