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新型Cu/低k芯片以其优异的性能逐步替代Al/SiO2芯片在微纳米器件中得到越来越多的应用。但由于其抗变形能力和强度较低,在引线键合中容易发生损坏。为研究Cu/低k芯片键合中的应力特征和失效机理,建立了Cu/低k芯片与传统Al/SiO2芯片铜引线键合过程的有限元分析模型,计算并对比分析了两种芯片中的应力状态。结果表明:芯片内应力在键合初期快速增长,随后继续增加,但增速变缓;键合过程中高应力区位于铜微球与芯片接触区边缘的下方,呈环形分布;振动中劈刀所在侧高应力区的范围及应力值明显大于另一侧;Cu/低k芯片中应力主要集中于Cu/低k层,Al/SiO2芯片中应力主要集中于劈刀所在侧的Si基板内。键合过程中应力在Cu/低k层的高度集中是新型芯片更易发生分层和开裂失效的根本原因。
The new Cu / low-k chips have been increasingly used in micro-nano devices due to their superior performance in gradually replacing Al / SiO2 chips. However, due to its resistance to deformation and low strength, prone to damage in wire bonding. In order to study the stress characteristics and failure mechanism of Cu / low-k chip bonding, a finite element analysis model of copper bonding between Cu / low-k chip and traditional Al / SiO2 chip was established. The two chips The stress state. The results show that the internal stress increases rapidly at the initial stage of bonding, and then increases continuously, but the growth rate becomes slower. During the bonding process, the high stress area is located under the edge of the contact area between the copper microsphere and the chip, In the Cu / low-k chip, the stress mainly concentrates on the Cu / low-k layer. The stress in the Al / SiO2 chip is mainly concentrated in the Si substrate on the side where the riving knife is located. The high concentration of stress in the Cu / low-k layer during bonding is the root cause of the new chip being more susceptible to delamination and cracking.