论文部分内容阅读
基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。
Based on a 65 nm CMOS process with a 1.2 V supply voltage, an analog-to-digital convertor (ADC) is designed with offset dual-channel technology. The chip test results show that the calibration method effectively eliminates and compensates the constraints of the performance of the pipeline ADC such as capacitance mismatch, interstage gain error and amplifier harmonic distortion. Pipelined ADC Increased signal-and-noise distortion ratio (SNRDR) from 28 dB before correction to 61 dB at 125 MS / s sample rate with a 3 MHz sine-wave input without spurious dynamic range (spurious-free dynamic range, SFDR) increased from 37 dB before correction to 62 dB. The ADC chip consumes 72 mW of power and has an area of 1.56 mm2. Offset dual-channel digital correction technology is implemented in computer software. The digital circuit consumes 12 mW of power and has an area of 0.21 mm2 at a 65-nm CMOS process at a 125-MHz clock.