日前,MathWorks宣布推出HDL Coder,它支持从MATLAB代码自动生成HDL代码,允许工程师用MATLAB语言实现FPGA和ASIC设计。同时发布的还有HDL Verifier,该产品包含用于测试的FPGA硬件在环功能。这两款产品使得MathWorks可提供利用MATLAB和Simulink进行HDL代码生成和验证的能力。 Recently, MathWorks announced the HDL Coder, which supports the automatic generation of HDL code from MATLAB code, allowing engineers to implement FPGA and ASIC designs in MATLAB language. Also released is HDL Verifier, which includes FPGA hardware in-loop capabilities for testing. These two products allow MathWorks to provide the ability to generate and validate HDL code using MATLAB and Simulink.