本设计所涉及的是一款计时器产品,其基于ARM内核,构建了计时器共用一个端口读写控制器与FPGA中央控制器进行数据通信。计时器内部工作是相互独立的,通过使用地址映射存储器使得计时器的指令执行更加高效;本设计还对中央控制器与计时器的通信时序和通信格式进行了优化,便于中央控制器对计时器的控制与测试。 This design involves a timer product, which is based on the ARM core, built a timer shared a port read and write controller and FPGA central controller for data communication. Timer internal work is independent of each other, through the use of address mapping memory makes the timer instruction execution more efficient; the design of the central controller and timer communication timing and communication format is optimized for the central controller timer Control and testing.