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在基于连续隐含Markov模型的嵌入式语音识别系统中,为提升计算效率、降低系统功耗,将算法中计算消耗最大的输出概率计算模块作为协处理器实现。通过先入先出队列电路隔离输出概率计算中的Markov距离和对数加法的数据通路使得系统参数可以灵活配置,并根据输出概率计算所需参数的地址产生规则设计了地址产生单元。采用Xilinx Virtex-5系列FPGA实现了该输出概率协处理器,并通过S3C44B0X微控制器验证了该设计。在配置参数为3维Gauss混合分量、27维特征矢量的条件下,对358个状态,协处理器工作在27MHz的时钟频率时计算输出概率的处理速度达到了0.13倍实时。
In the embedded speech recognition system based on continuous implicit Markov model, in order to improve the computational efficiency and reduce the system power consumption, the calculation module of output probability which is the most consumed in the algorithm is implemented as a coprocessor. Through the first-in-first-out queue circuit isolation output probability calculation Markov distance and logarithmic addition of the data path makes the system parameters can be flexibly configured, and the output probability of the required parameters of the address generation rules designed address generation unit. The output probability coprocessor was implemented using a Xilinx Virtex-5 family of FPGAs and verified with an S3C44B0X microcontroller. Under the condition that the configuration parameters are 3-dimensional Gauss mixed components and 27-dimensional eigenvector, the output probability of 358 states and coprocessor work at 27MHz clock speed is 0.13 times real-time.