Synopsys公司最近在其可测性设计(DFT)和自动测试图形生成(ATPG)产品中,利用其DFTCompiler工具的新功能,使设计人员可以对几百万门的SoC进行测试。此外,该公司新的TetraMAX(R)ATPG延迟测试工具,能够帮助测试人员在制造测试期间拥有检测与定时相关缺陷的综合能力。随着ASIC和SoC尺寸不断缩小,复杂性不断提高,能否有效地对这些器件实施测试,是设计人员面临的一 Synopsys Inc. recently leverages the new capabilities of its DFTCompiler tools in its testability design (DFT) and automated test pattern generation (ATPG) products to enable designers to test millions of SoCs. In addition, the company’s new TetraMAX (R) ATPG latency test tool helps testers have the combined ability to detect timing-related defects during manufacturing testing. As ASICs and SoCs continue to shrink in size and complexity, the ability to effectively test these devices is one of the