The analytical modeling of nanoscale devices is an important area of computer-aided design for fast and accurate nanoelectronic design and optimization.In the present paper,a new approach for modeling semiconductor devices,nanoscale double gate DG MOSFETs,by use of the gradual channel approximation(GC) approach and genetic algorithm optimization technique(GA) is presented.The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction,to achieve reliable,accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance,threshold voltage shift,quantum inversion charge density and drain current.These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations.The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage. The analytical modeling of nanoscale devices is an important area of ​​computer-aided design for fast and accurate nanoelectronic design and optimization. In the present paper, a new approach for modeling semiconductor devices, nanoscale double gate DG MOSFETs, by use of the gradual channel approximation (GC) approach and genetic algorithm optimization technique (GA) is presented. The proposed approach combines the universal optimization and fitting capability of GA and the cost-effective optimization concept of quantum correction, to achieve reliable, accurate and simple compact models for nanoelectronic circuit simulations.Our compact models give good predictions of the quantum capacitance, threshold voltage shift, quantum inversion charge density and drain current. These models have been verified with 2D self-consistent results from numerical calculations of the coupled Poisson-Schrodinger equations. The developed models can also be incorporated into nanoelectronic circuit simulators to study the nanoscale CMOS-based devices without impact on the computational time and data storage.