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介绍了一种带ESD瞬态检测的VDD-VSS之间的电压箝位结构,归纳了在设计全芯片ESD保护结构时需要注意的关键点;提出了一种亚微米集成电路全芯片ESD保护的设计方案,从实例中验证了亚微米集成电路的全芯片ESD保护设计。
A voltage clamping structure between VDD and VSS with ESD transient detection is introduced. The key points to be observed when designing a full-chip ESD protection structure are summarized. A full sub-micron integrated circuit ESD protection The design scheme verifies the full-chip ESD protection design of submicron integrated circuits from the examples.