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As semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the degradation and prolong systems lifetime. Negative Bias Temperature Insta-bility (NBTI) is emerging as one of the major reliability concerns. Two software tools for NBTI ana-lyzing are proposed in this paper, one for transistor-level, and the other for gate-level. The transis-tor-level can be used to estimate the delay degradation due to NBTI effect very accurately, while the gate-level can be used for repeat analysis in circuit optimization because of its fast computing speed.