根据3GPP的规定提出了TD-SCDMA网络测试平台中的Viterbi译码器的DSP实现方案。该方案兼顾了资源消耗和译码效率,提高了译码器的硬件结构和整体性能.通过对TD-SCDMA终端维特比译码的理解,设计出相应网络测试平台中的译码器。并给出了其DSP实现程序,利用CCS集成环境平台和TMS320C55XDSP芯片进行仿真分析。由仿真和测试结果表明,该实现方法在实际应用中检测效果很好。 According to the provisions of 3GPP, a DSP implementation of Viterbi decoder in TD-SCDMA network test platform is proposed. The scheme takes into account resource consumption and decoding efficiency and improves the hardware structure and overall performance of the decoder.Through the understanding of Viterbi decoding of TD-SCDMA terminal, the decoder in the corresponding network test platform is designed. And given its DSP implementation procedures, the use of CCS integrated environment platform and TMS320C55XDSP chip for simulation analysis. The simulation and test results show that this method is effective in practical application.