论文部分内容阅读
数字闭环加速度计可以解决传统模拟加速度计在输出电流到数字量(I/D)转换中带来的精度损失问题,而为实现数字闭环需将加速度计表头进行离散化。针对这一问题提出了一种表头离散化方法,将石英摆片、采样开关与零阶保持器整体离散化。建立数字闭环系统离散域数学模型,基于此模型进行仿真研究,仿真表明:此离散化方法可行,系统阶跃响应超调在10%左右,闭环带宽达到300 Hz以上。将其应用在数字闭环加速度计的实验系统,验证了仿真结果,为数字闭环加速度计的深入研究提供必要的理论指导和实验基础。
Digital closed-loop accelerometers solve the accuracy penalty of traditional analog accelerometers in the output current-to-digital (I / D) conversion, which necessitates the discretization of the accelerometer head for digital closed-loop. In order to solve this problem, a method of header discretization is proposed, which discretizes the quartz pendulum, sampling switch and zero-order holder. The mathematical model of the closed-loop digital closed-loop system is established. Based on this model, the simulation is conducted. The simulation shows that this discretization method is feasible. The overshoot of the system step response is about 10% and the closed-loop bandwidth is over 300 Hz. The experimental results verify the simulation results and provide the necessary theoretical guidance and experimental basis for the further study of digital closed-loop accelerometer.