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设计了一种可快速锁定、具有固定带宽比和良好抖动性能的自偏置锁相环。采用增加VCO延迟单元输出节点放电时间常数的方法,对VCO进行优化设计,获得良好的抖动性能。基于0.25μm混合信号CMOS工艺进行设计和仿真,在2.5 V电源供电条件下,锁相环的工作频率范围为600~1 500 MHz,在1 250 MHz输出频率的峰峰值抖动为14.3 ps,核心电路功耗为44mW。在不同工艺条件下的仿真结果表明,PLL在不同工艺条件下均具有良好的抖动性能。
A self-bias PLL with fast lock, fixed bandwidth ratio and good jitter performance is designed. The method of increasing the discharge time constant of the output node of the VCO delay unit is adopted to optimize the VCO and obtain good jitter performance. Based on a 0.25μm mixed-signal CMOS process design and simulation, the operating frequency range of the PLL is 600 to 1 500 MHz under 2.5 V supply and 14.3 ps for the peak-to-peak output at 1 250 MHz output frequency. The core circuit Power consumption is 44mW. The simulation results under different process conditions show that the PLL has good jitter performance under different process conditions.