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提出一种应用于10位逐次逼近型模数转换器(SAR ADC)的高精度比较器,具有精度高、功耗低的特点。该比较器采用差分结构的前置放大电路,提高输入信号的精度,其自身隔离效果减小了锁存器的回踢噪声和失调电压。动态锁存电路采用两级正反馈,有效提高比较器的响应速度。输出缓冲级电路增强输出级的驱动能力,调整输出波形。该比较器电路采用SMIC 65 nm CMOS工艺技术实现,使用Cadence公司Spectre系列软件对进行仿真,设置工作电压2.5 V,采样频率2 MHz,仿真结果表明,比较器的分辨率是0.542 5 mV,精度达到11位,失调电压为1.405μV,静态功耗为63μW,已成功应用于10位SAR ADC。
A high-precision comparator applied to a 10-bit successive approximation analog-to-digital converter (SAR ADC) is proposed with high accuracy and low power consumption. The comparator differential amplifier structure used to improve the accuracy of the input signal, the isolation effect of the latch to reduce the back-kick noise and offset voltage. Dynamic latch circuit uses two positive feedback, effectively improve the response speed of the comparator. Output buffer circuit enhances output stage drive capability, adjust the output waveform. The comparator circuit is implemented in SMIC 65 nm CMOS process technology using a Cadence Spectre series software to simulate an operating voltage of 2.5 V with a sampling frequency of 2 MHz. The simulation results show that the resolution of the comparator is 0.542 5 mV with accuracy of 11-bit, offset voltage of 1.405μV, static power dissipation of 63μW, has been successfully applied to 10-bit SAR ADC.